Complex Programmable Logic Device (CPLD) featuring 1700 Macro Cells and 2210 Device Logic Cells. This CPLD operates at up to 201.1MHz with 0.18um process technology and a typical 1.8V supply voltage. It offers 272 user I/Os and is housed in a 324-pin Fine Pitch Ball Grid Array (FBGA) package for surface mounting. In-system programmability is supported, with an operating temperature range of 0°C to 85°C.
PackageFBGA
MountingSurface Mount
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Technical Specifications
Intel EPM2210GF324C5NES technical specifications.
General
Basic Package Type
Ball Grid Array
Package Family Name
BGA
Package/Case
FBGA
Package Description
Fine Pitch Ball Grid Array
Lead Shape
Ball
Pin Count
324
PCB
324
Package Length (mm)
19
Package Width (mm)
19
Package Height (mm)
1.25
Seated Plane Height (mm)
1.75
Pin Pitch (mm)
1
Package Material
Plastic
Mounting
Surface Mount
Jedec
MS-034AAG-1
Family Name
MAX® II
Device Logic Cells
2210
Number of User I/Os
272
Number of Logic Blocks/Elements
221
Number of Macro Cells
1700
Program Memory Type
Flash
Process Technology
0.18um
Min Operating Temperature
0°C
Max Operating Temperature
85°C
Typical Operating Supply Voltage
1.8V
Min Operating Supply Voltage
1.71V
Programmability
Yes
In-System Programmability
Yes
Speed Grade
5
Compliance
Cage Code
4BA62
EU RoHS
Yes
HTS Code
8542390001
Schedule B
8542390000
Automotive
No
AEC Qualified
No
PPAP
No
Radiation Hardening
No
RoHS Versions
2002/95/EC
Datasheet
Intel EPM2210GF324C5NES Datasheet
Download the complete datasheet for Intel EPM2210GF324C5NES to view detailed technical specifications.
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