Complex Programmable Logic Device (CPLD) from the MAX® II family, featuring 192 macro cells and 240 device logic cells. This surface-mount component utilizes 0.18um process technology and offers 80 user I/Os. It operates with a typical supply voltage of 2.5V or 3.3V and has a speed grade of 5. Packaged in a 100-pin Thin Profile Fine Pitch Ball Grid Array (TFBGA) measuring 11x11x1mm, it supports in-system programmability and operates within a temperature range of 0°C to 85°C.
PackageTFBGA
MountingSurface Mount
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Technical Specifications
Intel EPM240F100C5NES technical specifications.
General
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | TFBGA |
| Package Description | Thin Profile Fine Pitch Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 100 |
| PCB | 100 |
| Package Length (mm) | 11 |
| Package Width (mm) | 11 |
| Package Height (mm) | 1 |
| Seated Plane Height (mm) | 1.4 |
| Pin Pitch (mm) | 1 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Jedec | MO-192DAC-1 |
| Family Name | MAX® II |
| Device Logic Cells | 240 |
| Number of User I/Os | 80 |
| Number of Logic Blocks/Elements | 24 |
| Number of Macro Cells | 192 |
| Program Memory Type | Flash |
| Process Technology | 0.18um |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 85°C |
| Typical Operating Supply Voltage | 2.5|3.3V |
| Min Operating Supply Voltage | 2.375V |
| Programmability | Yes |
| In-System Programmability | Yes |
| Speed Grade | 5 |
Compliance
| Cage Code | 4BA62 |
| EU RoHS | Yes |
| HTS Code | 8542390001 |
| Schedule B | 8542390000 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2002/95/EC |
Datasheet
Intel EPM240F100C5NES Datasheet
Download the complete datasheet for Intel EPM240F100C5NES to view detailed technical specifications.
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