Complex Programmable Logic Device (CPLD) featuring 440 macro cells and 57 logic elements. This device offers 76 user I/Os and is built on 0.18um process technology. Operating at 2.5V/3.3V, it provides in-system programmability and a speed grade of 5. The component is housed in a 100-pin Thin Fine Pitch Ball Grid Array (TFBGA) package, suitable for surface mounting.
PackageTFBGA
MountingSurface Mount
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Technical Specifications
Intel EPM570F100I5NES technical specifications.
General
Basic Package Type
Ball Grid Array
Package Family Name
BGA
Package/Case
TFBGA
Package Description
Thin Fine Pitch Ball Grid Array
Lead Shape
Ball
Pin Count
100
PCB
100
Package Length (mm)
11
Package Width (mm)
11
Package Height (mm)
1
Seated Plane Height (mm)
1.4
Pin Pitch (mm)
1
Package Material
Plastic
Mounting
Surface Mount
Jedec
MO-192DAC-1
Family Name
MAX® II
Device Logic Cells
570
RAM Bits
0Kbit
Number of User I/Os
76
Number of Logic Blocks/Elements
57
Number of Macro Cells
440
Program Memory Type
Flash
Process Technology
0.18um
Min Operating Temperature
-40°C
Max Operating Temperature
100°C
Typical Operating Supply Voltage
2.5|3.3V
Min Operating Supply Voltage
2.375V
Programmability
Yes
In-System Programmability
Yes
Speed Grade
5
Compliance
Cage Code
4BA62
EU RoHS
Yes
HTS Code
8542390001
Schedule B
8542390000
Automotive
No
AEC Qualified
No
PPAP
No
Radiation Hardening
No
RoHS Versions
2002/95/EC
Datasheet
Intel EPM570F100I5NES Datasheet
Download the complete datasheet for Intel EPM570F100I5NES to view detailed technical specifications.
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