Complex Programmable Logic Device (CPLD) featuring 440 macro cells and 57 logic elements. This device offers 160 user I/Os and operates at a maximum frequency of 247.5MHz. Built on 0.18um process technology, it utilizes Flash for program memory and supports in-system programmability. The CPLD is housed in a 256-pin Fine Pitch Ball Grid Array (FBGA) package with a 1mm pin pitch, designed for surface mounting. It operates within a voltage range of 1.71V to 1.8V and functions across an industrial temperature range of -40°C to 100°C.
PackageFBGA
MountingSurface Mount
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Technical Specifications
Intel EPM570GF256I4NES technical specifications.
General
Basic Package Type
Ball Grid Array
Package Family Name
BGA
Package/Case
FBGA
Package Description
Fine Pitch Ball Grid Array
Lead Shape
Ball
Pin Count
256
PCB
256
Package Length (mm)
17
Package Width (mm)
17
Package Height (mm)
1.25
Seated Plane Height (mm)
1.75
Pin Pitch (mm)
1
Package Material
Plastic
Mounting
Surface Mount
Jedec
MS-034AAF-1
Family Name
MAX® II
Device Logic Cells
570
RAM Bits
0Kbit
Number of User I/Os
160
Number of Logic Blocks/Elements
57
Number of Macro Cells
440
Program Memory Type
Flash
Process Technology
0.18um
Min Operating Temperature
-40°C
Max Operating Temperature
100°C
Typical Operating Supply Voltage
1.8V
Min Operating Supply Voltage
1.71V
Programmability
Yes
In-System Programmability
Yes
Speed Grade
4
Compliance
Cage Code
4BA62
EU RoHS
Yes
HTS Code
8542390001
Schedule B
8542390000
Automotive
No
AEC Qualified
No
PPAP
No
Radiation Hardening
No
RoHS Versions
2011/65/EU
Datasheet
Intel EPM570GF256I4NES Datasheet
Download the complete datasheet for Intel EPM570GF256I4NES to view detailed technical specifications.
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