
Complex Programmable Logic Device (CPLD) featuring 440 macro cells and 57 logic elements. This device offers 160 user I/Os and operates at a maximum frequency of 247.5MHz. Built on 0.18um process technology, it utilizes Flash for program memory and supports in-system programmability. The CPLD is housed in a 256-pin Fine Pitch Ball Grid Array (FBGA) package with a 1mm pin pitch, designed for surface mounting. It operates within a voltage range of 1.71V to 1.8V and functions across an industrial temperature range of -40°C to 100°C.
Intel EPM570GF256I4NES technical specifications.
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