The communications controller integrates a CPU32+ processor, system integration logic, and a communications processor module on one chip. It supports a 32-bit internal bus, up to a 32-bit external data bus, and up to 32 address lines. The device provides four serial communications controllers, two serial management controllers, one SPI port, two independent DMA channels, and fourteen serial DMA channels. Operation supports static system clocking up to 25 MHz, with documented 25 MHz and 33.34 MHz timing variants in the reference manual. Family package options include 241-lead PGA and 240-lead PQFP versions.
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| Processor core | CPU32+ |
| Processor performance | 4.5 at 25 MHzMIPS |
| Internal bus width | 32bit |
| External data bus width | 8, 16, or 32bit |
| Address lines | Up to 32, at least 28 always available |
| System frequency | 0 to 25 static operationMHz |
| Serial communications controllers | 4 SCCs |
| Serial management controllers | 2 SMCs |
| SPI ports | 1 |
| Independent DMA channels | 2 |
| Serial DMA channels | 14 |
| Buffer descriptors | 224 |
| Dual-port RAM | 2.5KB |
| General-purpose timers | Four 16-bit timers or two 32-bit timers |
| External IRQ lines | 7 |
| Supply voltage | 4.75 to 5.25 or 3.0 to 3.6V |
| Operating ambient temperature | 0 to 70 or -40 to 85 for CQFP and PGA variants°C |
| Package options | 241-lead PGA and 240-lead PQFP |
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