The 24-bit digital signal processor uses a DSP56000 core with on-chip program and data memories. It supports up to 40 MIPS at an 80 MHz clock and includes a 24 by 24-bit multiply-accumulate datapath with two 56-bit accumulators. Integrated peripherals include a synchronous serial interface, serial communications interface, host interface, 24-bit timer/event counter, PLL clock generation, GPIO, and OnCE debug support. The device operates from a 5 V supply and was offered in 132-pin PQFP, 144-pin TQFP, and 132-pin ceramic PGA package options.
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| Processor core | 24-bit DSP56000 |
| Maximum instruction rate | 40MIPS |
| Maximum core clock frequency | 80MHz |
| Instruction cycle time at 80 MHz | 25ns |
| Maximum operations rate | 240MOPS |
| Program RAM | 512 x 24words x bits |
| Bootstrap ROM | 64 x 24words x bits |
| Data RAM | 2 x 256 x 24words x bits |
| Data ROM | 2 x 256 x 24words x bits |
| External address bus width | 16bits |
| External data bus width | 24bits |
| Accumulator width | 56bits |
| MAC operation | 24 x 24 + 56 to 56bits |
| Host interface | Byte-wide with DMA support |
| Serial interfaces | SSI and full-duplex SCI |
| Timer | One 24-bit timer/event counter |
| GPIO count | Up to 25pins |
| Supply voltage | 4.5 to 5.5V |
| Junction operating temperature range | -40 to 105°C |
| Package options | 132-pin PQFP; 144-pin TQFP; 132-pin ceramic PGA |
These are design resources that include the NXP DSP56002
An application note describing hardware and software methods for Ethernet address filtering using NXP QUICC and PowerQUICC communication controllers.
