Secure Arm Cortex-M33 microcontroller family combines low-power operation with integrated security features for IoT silicon designs. The architecture includes Arm TrustZone isolation, an SRAM PUF-based root of trust, secure provisioning, and asset protection. It supports real-time execution from encrypted images stored in internal flash. The certified configuration uses LPC55S00 A0 hardware with TF-M firmware and RTX v5 RTOS for PSA Certified Level 1 evaluation.
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| Processor core | Arm Cortex-M33 |
| Security isolation | Arm TrustZone |
| Root of trust | SRAM PUF-based |
| Secure provisioning | Supported |
| Encrypted image execution | Internal flash |
| Hardware version | A0 |
| RTOS used for certification | RTX v5 |
| Firmware used for certification | TF-M v1.0 Beta |
| API test suite version | 0.8 |
| Psa Certified | Level 1 vBeta 002, certificate 0604565272911-10010 |
These are design resources that include the NXP LPC55S00
Technical guide for flash memory operations on NXP LPC5500 MCUs, covering ROM APIs, Protected Flash Regions (PFR), and ECC-related HardFault prevention.
