The integrated processor combines a CPU32 32-bit M68000-compatible core with a two-channel DMA controller and on-chip peripheral subsystems. It supports 32 address lines, 16 data lines, two 16-bit timer/counters, four chip selects, and a two-channel USART compatible with the MC68681 and MC2681 DUART. The 25 MHz device is supplied in a 144-lead QFP package measuring 28 mm by 28 mm with 0.65 mm pitch. The exact orderable device is not EU RoHS compliant, is not Pb-free, is not halogen-free, and has an MSL 4 moisture sensitivity rating.
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| Processor core | CPU32, MC68020-derived 32-bit CPU |
| Architecture compatibility | M68000, MC68000 and MC68010 object-code compatible |
| Maximum operating frequency | 25MHz |
| Performance | 4.8MIPS |
| DMA channels | 2 |
| DMA address width | 32bit |
| DMA data transfer widths | 8, 16, 32bit |
| DMA sustained transfer rate | 50 single-address; 12.5 memory-to-memoryMbyte/s |
| Serial interface | Two-channel full-duplex USART, MC68681/MC2681 compatible |
| Serial maximum transfer rate | 9.8Mbit/s |
| Timers | Two independent 16-bit counter/timers |
| Timer resolution | 80 at 25 MHzns |
| Address bus width | 32bit |
| Data bus width | 16bit |
| Chip selects | 4 programmable |
| Package | 144-lead QFP, 28 mm x 28 mm x 3.6 mm, 0.65 mm pitch |
| Package weight | 5.7375g |
| Moisture sensitivity level | MSL 4 |
| Peak processing temperature | 220°C |
| EU RoHS | No |
| Pb Free | No |
| Halogen Free | No |
| Rohs Directive | 2011/65/EU |
| Rohs Declaration | Does not contain RoHS restricted substances except for lead in solders and selected exemptions |
| Plating Indicator | e0 |
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These are design resources that include the NXP MC68340CFT25E
Errata and ordering information addendum for the NXP MC68340 integrated processor, covering package types, RoHS status, temperature ranges, and operating frequencies.
