The integrated processor combines a CPU32 M68000-compatible 32-bit core with a two-channel DMA controller and on-chip peripheral subsystems. It supports a 16-bit external data bus, 32 address lines, two-channel USART, two independent counter/timers, system integration logic, and IEEE 1149.1 boundary scan. The 25 MHz standard-voltage family operates from a 5 V supply and supports high-speed DMA transfers up to 50 Mbytes per second in single-address mode. The device is intended for embedded control and general computing systems requiring integrated processing, serial I/O, timers, bus arbitration, and system-protection functions.
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| Core | CPU32, MC68020-derived 32-bit central processor unit |
| Maximum clock frequency | 25.16MHz |
| Supply voltage | 5.0 ±5%V |
| Address bus width | 32bit |
| External data bus width | 16bit |
| DMA channels | 2 |
| DMA address width | 32bit |
| DMA transfer sizes | 8, 16, 32bit |
| Maximum DMA transfer rate | 50 single-address mode; 12.5 memory-to-memory at 25.16 MHzMbyte/s |
| Serial interface | Two-channel USART |
| Maximum serial transfer rate | 9.8Mbit/s |
| Counter/timers | 2 independent 16-bit counter/timers |
| Timer resolution | 80 at 25 MHzns |
| General-purpose I/O | Up to 16 discrete I/O lineslines |
| Boundary scan | IEEE 1149.1 JTAG |
| Operating temperature range | 0 to 70 or -40 to 85, depending on orderable suffix°C |
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These are design resources that include the NXP MC68340CPV25E
Errata and ordering information addendum for the NXP MC68340 integrated processor, covering package types, RoHS status, temperature ranges, and operating frequencies.
