The QUICC communications controller integrates a 32-bit CPU32+ processor core with communications and system-integration peripherals. It operates from 0 MHz to 25 MHz and delivers approximately 4.5 MIPS at 25 MHz. The device provides up to a 32-bit data bus, up to 32 address lines, an eight-bank memory controller, four SCCs, two SMCs, one SPI, two independent DMA channels, and fourteen serial DMA channels. It supports Ethernet on SCC1, HDLC/SDLC, UART, synchronous UART, BISYNC, transparent modes, time-slot assignment, and two TDM channels.
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| Processor Core | CPU32+ |
| Architecture Width | 32bit |
| Operating Frequency | 0 to 25MHz |
| Performance | 4.5 at 25 MHzMIPS |
| Data Bus Width | Up to 32bit |
| Address Lines | Up to 32 |
| Memory Controller Banks | 8 |
| General-Purpose Timers | Four 16-bit or two 32-bit |
| Independent DMA Channels | 2 |
| Serial DMA Channels | 14 |
| Dual-Port RAM | 2.5KB |
| Serial Communication Controllers | 4 SCCs |
| Serial Management Controllers | 2 SMCs |
| Serial Peripheral Interface | 1 SPI, master/slave and multimaster capable |
| Ethernet Support | 10 on SCC1Mbps |
| HDLC/SDLC Support | 2 on all four SCC channelsMbps |
| External Interrupt Lines | 7 |
| Package Options | 241-lead PGA and 240-lead PQFP |
These are design resources that include the NXP MC68MH360
Comprehensive user manual for the MC68360 QUICC, detailing its CPU32+ core, Communication Processor Module (CPM), and System Integration Module (SIM60) for network applications.
