Power Architecture communications processor integrates an e300c3 core running up to 400 MHz with 16 KB instruction and 16 KB data caches. The device supports a 16- or 32-bit DDR1/DDR2 SDRAM controller, dual enhanced three-speed Ethernet controllers, dual SATA 3 Gbps controllers, dual single-lane PCI Express interfaces, PCI, USB 2.0, TDM, I2C, SPI, DUART, local bus and GPIO interfaces. Its SEC 3.3 security engine accelerates RSA, Diffie-Hellman, ECC, DES, 3DES, AES, SHA, MD5, HMAC, random-number generation and CRC operations. The processor is supplied in a 620-interconnect 29 mm by 29 mm TEPBGA II package with 1 mm pitch.
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| CPU core | e300c3 Power Architecture |
| Maximum core frequency | 400MHz |
| Instruction cache | 16KB |
| Data cache | 16KB |
| DDR memory bus width | 16 or 32bit |
| DDR memory data rate | 266MHz |
| Ethernet controllers | Two enhanced three-speed 10/100/1000 Mbps eTSECs |
| SATA controllers | Two SATA 1.5/3.0 Gbps controllers |
| PCI Express interfaces | Two PCI Express 1.0a x1 interfaces |
| PCI interface | 32-bit PCI 2.3 up to 66 MHz |
| USB interface | USB 2.0 high-speed host/device/OTG with on-chip PHY |
| Security engine | SEC 3.3 with AES, DES, 3DES, RSA, Diffie-Hellman, ECC, SHA, MD5, HMAC, RNG and CRC acceleration |
| Core supply voltage | 1.0 ± 0.05V |
| DDR I/O voltage | 1.8 ± 0.1 or 2.5 ± 0.2V |
| Standard I/O voltage | 3.3 ± 0.3V |
| Package outline | 29 x 29mm |
| Package interconnects | 620 |
| Ball pitch | 1mm |
| Typical module height | 2.23mm |
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These are design resources that include the NXP MPC8315E
Errata document for the MPC8315E PowerQUICC II Pro Reference Manual detailing corrections for System PLL registers, DDR memory controller configuration, and USB interface registers.
