32-bit RISC microprocessor, PowerQUICC III MPC85xx Processor family, featuring a 1.333GHz maximum speed and dual e500 cores. This surface-mount device utilizes a 0.09um process technology and offers 32KB instruction and 32KB data cache. Housed in a 1023-pin Flip Chip Ball Grid Array (FCBGA) package with a 1mm pin pitch, it operates across a 1.8V/2.5V/3.3V supply range and supports I2C and UART interfaces. Operating temperature range is -40°C to 105°C.
PackageFCBGA
MountingSurface Mount
Quick Jump:
Technical Specifications
NXP MPC8572ECLPXAULD technical specifications.
General
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | FCBGA |
| Package Description | Flip Chip Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 1023 |
| PCB | 1023 |
| Package Length (mm) | 33 |
| Package Width (mm) | 33 |
| Package Height (mm) | 2.78(Max) |
| Seated Plane Height (mm) | 3.38(Max) |
| Pin Pitch (mm) | 1 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Family Name | PowerQUICC III MPC85xx Processor |
| Data Bus Width | 32bit |
| Instruction Set Architecture | RISC |
| Device Core | e500 |
| Maximum Speed | 1333MHz |
| Process Technology | 0.09um |
| Number of CPU Cores | 2 |
| Interface Type | I2C/UART |
| CAN | 0 |
| UART | 2 |
| USART | 0 |
| I2C | 1 |
| SPI | 0 |
| USB | 0 |
| Ethernet | 0 |
| I2S | 0 |
| Max Operating Supply Voltage | 1.155V |
| Min Operating Temperature | -40°C |
| Max Operating Temperature | 105°C |
| Instruction Cache Size | 32KB |
| Data Cache Size | 32KB |
| Multiply Accumulate | No |
| Ethernet Speed | 10Mbps/100Mbps/1000Mbps |
Compliance
| Cage Code | H1R01 |
| EU RoHS | No |
| HTS Code | 8542310001 |
| Schedule B | 8542310000 |
| ECCN | 5A002.a |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2011/65/EU, 2015/863 |
Datasheet
NXP MPC8572ECLPXAULD Datasheet
Download the complete datasheet for NXP MPC8572ECLPXAULD to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.