32-bit RISC microprocessor, PowerQUICC III MPC85xx family, featuring a single e500 core operating at up to 1000 MHz. This surface-mount device utilizes a 0.09um process technology and offers 32KB instruction and 32KB data cache. Connectivity includes multiple Ethernet interfaces (MII/RMII/RGMII/SGMII) supporting 10/100/1000Mbps, along with I2C, SPI, UART, and USB interfaces. Packaged in a 783-pin FCBGA with dimensions of 29x29x2.2mm, it operates from 0°C to 105°C.
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NXP PPC8536EDVTAQG technical specifications.
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | FCBGA |
| Package Description | Flip Chip Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 783 |
| PCB | 783 |
| Package Length (mm) | 29 |
| Package Width (mm) | 29 |
| Package Height (mm) | 2.2(Max) |
| Seated Plane Height (mm) | 2.76(Max) |
| Pin Pitch (mm) | 1 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Family Name | PowerQUICC III MPC85xx Processor |
| Data Bus Width | 32bit |
| Instruction Set Architecture | RISC |
| Device Core | e500 |
| Maximum Speed | 1000MHz |
| Process Technology | 0.09um |
| Core Architecture | e500 |
| Number of CPU Cores | 1 |
| Interface Type | Ethernet/I2C/SPI/UART/USB |
| CAN | 0 |
| UART | 2 |
| USART | 0 |
| I2C | 2 |
| SPI | 1 |
| USB | 3 |
| Ethernet | 2 |
| I2S | 0 |
| Max Operating Supply Voltage | 1.05|1.155V |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 105°C |
| Instruction Cache Size | 32KB |
| Data Cache Size | 32KB |
| Multiply Accumulate | No |
| Ethernet Interface Type | MII/RMII/RGMII/SGMII |
| Ethernet Speed | 10Mbps/100Mbps/1000Mbps |
| Cage Code | H1R01 |
| EU RoHS | Yes with Exemption |
| HTS Code | 8542310001 |
| Schedule B | 8542310000 |
| ECCN | 5A002 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2011/65/EU, 2015/863 |
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