Crossover microcontroller family integrates an Arm Cortex-M33 core with a Cadence Tensilica Fusion F1 DSP for low-power wearable and consumer IoT designs. The Cortex-M33 and Fusion DSP each run at up to 275 MHz, with up to 5 MB of system SRAM and dual 32 KB FlexSPI caches. Integrated peripherals include USB high-speed host and device, SD/eMMC interfaces, FlexComm serial modules, I3C buses, a digital microphone interface, parallel camera and display interfaces, MIPI DSI, and 2D graphics acceleration.
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| CPU core | Arm Cortex-M33 |
| CPU maximum frequency | 275MHz |
| DSP core | Cadence Tensilica Fusion F1 |
| DSP maximum frequency | 275MHz |
| System SRAM | Up to 5MB |
| FlexSPI cache | 2 x 32KB |
| DMA engines | 2 engines, 32 channels each |
| Security features | Arm TrustZone, MPU, CASPER crypto coprocessor |
| Math accelerator | PowerQuad fixed and floating-point DSP accelerator |
| Graphics acceleration | 2D GPU with vector graphics acceleration |
| USB interface | High-speed host/device controller with on-chip PHY |
| Serial interfaces | Up to 12 FlexComm modules configurable as SPI, I2C, I2S, or UART |
| High-speed SPI | 50MHz |
| I3C interfaces | 2 |
| Digital microphone channels | Up to 8 |
| Memory card interfaces | 2 SD/eMMC, one supporting eMMC 5.0 HS400/DDR |
| Camera interface | 8/10/16-bit parallel CSI via FlexIO |
| Display interfaces | 8/10/16/18/24-bit parallel LCD via FlexIO and MIPI DSI |
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These are design resources that include the NXP RT500
Guide for increasing i.MX RT500 MCU Free-Running Oscillator (FRO) frequency from 192 MHz to 250 MHz to enhance performance in battery-powered applications.
Guide on configuring secure GPIO and the SEC_GPIO_MASK in NXP RT500 microcontrollers to prevent information leakage between secure and non-secure TrustZone domains.
Technical guide for implementing ARM TrustZone security on NXP RT500 MCUs, covering SAU/IDAU configuration, secure bus control, and memory attribution for Cortex-M33 cores.
