This dual-channel isolated gate driver uses capacitive coupling and provides 2.5 kVrms input-to-output isolation. It delivers 3.5 A and 6.5 A peak gate-drive capability across two channels in a 16-pin SOIC narrow-body package. The device accepts 3.3 V to 20 V bias and signal levels on the input side and supports up to 32 V bias on the output side. Typical rise and fall times are 12 ns and 10 ns, maximum propagation delay is 80 ns, and maximum pulse-width distortion is 20 ns. It operates over a -40 °C to 125 °C ambient temperature range and specifies minimum common-mode transient immunity of 100 kV/µs.
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Onsemi NCD57255 technical specifications.
| Technology | Capacitive Coupling |
| Number of Channels | 2 |
| Isolation Voltage | 2500Vrms |
| Peak Output Current Source | 3.5A |
| Peak Output Current Sink | 6.5A |
| Output Current High | 3.5A |
| Output Current Low | 3.5A |
| Input Side Bias Voltage Min | 3.3V |
| Input Side Bias Voltage Max | 20V |
| Output Side Bias Voltage Max | 32V |
| Operating Temperature Min | -40°C |
| Operating Temperature Max | 125°C |
| Propagation Delay tpLH Max | 80ns |
| Propagation Delay tpHL Max | 80ns |
| Pulse Width Distortion Max | 20ns |
| Rise Time Typ | 12ns |
| Fall Time Typ | 10ns |
| Common Mode Transient Immunity Min | 100kV/µs |
| Package | 16-SOIC Narrow Body |
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