Dual J-K Positive-Edge-Triggered Flip-Flops with Preset and Clear 16-SOIC 0 to 70

IC LS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, SO-16, FF/Latch
3-line to 8-line decoder / demultiplexer with address latches 16-CDIP 0 to 70
16 x 4 Synchronous FIFO Memory with Open-Collector Outputs 16-PDIP 0 to 70