The 32-bit integrated processor combines a CPU32 central processor, direct memory access, timers, serial communication, and system integration logic on one device. It operates at up to 25 MHz and uses a 144-LQFP package with a 20 mm by 20 mm body. The processor includes a two-channel DMA controller, a two-channel USART, two independent counter/timers, chip-select and wait-state generation, bus arbitration, and IEEE 1149.1 boundary scan support. Tray packaging is specified, and RoHS compliance is indicated for the orderable part.
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| CPU Core | CPU32 |
| Processor Width | 32bit |
| Maximum Clock Frequency | 25MHz |
| Data Bus Width | 16bit |
| Address Lines | 32 |
| DMA Channels | 2 |
| DMA Transfer Widths | 8, 16, 32bit |
| DMA Sustained Transfer Rate | 50Mbyte/s |
| USART Channels | 2 |
| USART Maximum Transfer Rate | 9.8Mbit/s |
| Counter/Timers | 2 |
| Timer Counter Width | 16bit |
| Timer Resolution | 80ns |
| Boundary Scan | IEEE 1149.1 JTAG |
| Package | 144-LQFP (20x20) |
| Packaging | Tray |
| RoHS | Compliant |
| ECCN | EAR99 |
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These are design resources that include the NXP MC68340AG25E
Errata and ordering information addendum for the NXP MC68340 integrated processor, covering package types, RoHS status, temperature ranges, and operating frequencies.
