
TELECOM-LINE EQUALIZER, QCC48, 7 X 7 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, LLP-48
125 MHz - 312.5 MHz FPGA-Link Serializer with DDR LVDS Parallel Interface 48-WQFN -40 to 85

125 MHz - 312.5 MHz FPGA-Link Serializer with DDR LVDS Parallel Interface 48-WQFN -40 to 85
125 MHz - 312.5 MHz FPGA-Link Serializer with DDR LVDS Parallel Interface 48-WQFN -40 to 85

125 MHz - 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface 48-WQFN -40 to 85
125 MHz - 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface 48-WQFN -40 to 85

125 MHz - 312.5 MHz FPGA-Link Serializer with DDR LVDS Parallel Interface 48-WQFN -40 to 85
125 MHz - 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface 48-WQFN -40 to 85