Intel
The following design aims at using a commonly available 82365SL register model compatible host controller.
Technical guide for interfacing Freescale MC68EC020 and 683XX processors with ISA-based PCMCIA host controllers like the 82365SL using PLD-based logic and byte lane swapping.
This application note (AN2043) provides a design for connecting NXP (Freescale) M68K-family processors, specifically the MC68EC020 and 683XX series (including MC68331 and MC68340), to Intel 82365SL-compatible PCMCIA host controllers. It details how to bridge the 68K bus with the ISA-style interface used by common PCMCIA controllers. Key technical challenges addressed include reconciling byte ordering differences (Big Endian to Little Endian) through byte lane swapping and mapping the 68K DSACK handshake to ISA bus timing. The design utilizes PLD or PAL-based bus interface logic to generate control signals for I/O and memory spaces while supporting dynamic bus sizing for 16-bit and 32-bit configurations.
Intel
The following design aims at using a commonly available 82365SL register model compatible host controller.
Freescale Semiconductor
If an integrated MCU such as the 68331 or 68340 is used, the address decode logic may be replaced by programmed chip selects.
| 82365SL | Intel | The following design aims at using a commonly available 82365SL register model compatible host controller. |
| MC68331 | Freescale Semiconductor | If an integrated MCU such as the 68331 or 68340 is used, the address decode logic may be replaced by programmed chip selects. |
| MC68340 | Freescale Semiconductor | device such as the 68340 which has DMA capability. |
| MC68EC020 | Freescale Semiconductor | The 68K target is an EC020 or CPU32-like bus. |