SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96, PLASTIC, LFBGA-96
25-Bit configurable registered buffer with address-parity test 96-LFBGA -40 to 85
25-Bit Configurable Registered Buffer with SSTL_18 Inputs and Outputs 96-LFBGA 0 to 70