PowerQUICC communications processor integrates a 32-bit Power Architecture core with communication and system-control peripherals. The processor operates at up to 80 MHz and supports 3.3 V operation with 5 V TTL-compatible I/O except EXTAL and EXTCLK. It includes instruction and data caches, MMUs, a memory controller, timers, interrupt resources, JTAG, Ethernet, ATM, SCC, SMC, SPI, I2C, PCMCIA, and low-power operating modes. The device is specified in a 357-pin ball grid array package.
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| Core architecture | 32-bit Power Architecture single-issue core |
| Maximum operating frequency | 80MHz |
| Data bus width | Up to 32bit |
| Address lines | 32 |
| Instruction cache | 4 or 16Kbyte |
| Data cache | 4 or 8Kbyte |
| TLB entries | 32-entry instruction and data TLBs |
| Memory controller banks | 8 |
| General-purpose timers | Four 16-bit or two 32-bit timers |
| External interrupt request lines | 7 |
| Ethernet support | 10/100 IEEE 802.3uMbps |
| ATM cell processing | 50 to 70 at 50 MHz system clockMbps |
| Dual-port RAM | Up to 8Kbyte |
| Serial DMA channels | 16 |
| Baud-rate generators | 4 |
| Serial communications controllers | 4 SCCs |
| Serial management channels | 2 SMCs |
| Peripheral interfaces | SPI, I2C, PCMCIA, JTAG |
| Operating voltage | 3.3 with 5 V TTL compatibility except EXTAL and EXTCLKV |
| Package | 357-pin ball grid array |
These are design resources that include the NXP MPC860
Technical guide for debugging and optimizing the Communication Processor Module (CPM) and Serial Communication Controller (SCC) on NXP MPC860 and MC68360 processors.
Application note for the CPM Interrupt Controller (CPIC) in NXP MPC860, MPC823, and MC68360 processors, detailing register configuration, prioritization, and interrupt handling.
Application note providing design guidelines for crystal feedback oscillators used with NXP MPC860, MC68360, and MC68302 processors, including self-oscillating circuit analysis.
An application note describing the implementation of True Little-Endian (TLE) mode in NXP MPC8xx processors to ensure compatibility with little-endian system agents.
An application note describing hardware and software methods for Ethernet address filtering using NXP QUICC and PowerQUICC communication controllers.
Technical overview of exception handling for NXP MPC860 EPPC, covering MSR settings, vector tables, exception classes, and processing sequences.
Technical guidance for the Communication Processor Module (CPM) in NXP MPC823 and MPC860 series, covering SCC configuration, buffer descriptors, SDMA behavior, and troubleshooting.
A technical guide to the System Interface Unit (SIU) interrupt controller for MPC823 and MPC860 processors, covering register configuration, priorities, and initialization.
