
3.3-V Phase-Lock Loop Clock Driver with Power Down Mode 24-TSSOP 0 to 85

PLL Clock Driver for Synch. DRAM & Gen. Purp. Apps W/Spread Spectrum Compatibility, Power Down Mode 8-TSSOP -40 to 85

2.5-V SSTL-II phase-lock loop clock driver for double data-rate synchronous DRAM applications 48-TSSOP 0 to 85