8-Bit D-Type Latch, 110MHz, 3-State, SOIC, CMOS
512b FIFO Memory, 60MHz, 9ns Access, 1b Word, 28-SOIC
512x18 Sync FIFO Memory, 15ns Access, 40MHz, 5V, SSOP
2Kx9 Asynchronous FIFO Memory, 15ns Access, 9-bit, PLCC
8-Bit Inverting D-Type Latch, 5V, 3-State, TSSOP-20
Dual D Flip-Flop, 210MHz, 5V, SSOP, CMOS Logic IC
3-Input AND Gate IC, 74ACT Series, CMOS, SSOP-14, 5V
Quad 2-Input AND Gate IC, 5V, 24mA, 9ns, TSSOP
512x18 Asynchronous FIFO Memory, 20ns Access, 18b, 9Kb, 5V, SSOP
18Kb 1Kx18 Synchronous FIFO, 13ns, 50MHz, 5V, PLCC
2Kx9 Asynchronous FIFO Memory, 22ns Access, 9b, 25MHz, 5V, PLCC
256x18 FIFO Memory, 20ns Access, 25MHz, 5V, SSOP
Hex Schmitt-Trigger Inverter IC, 5V, 12.5ns, 6 Gates, TSSOP
Hex Inverter IC, 6-Gate, 5V, CMOS, SOIC, -40 to 85°C
Hex Inverter IC, 6-Gate, 5V, 8.5ns, TSSOP
18Kb 18b Unidirectional FIFO IC, 40MHz, 5V, LQFP
1024 x 9 x 2 Asynchronous Bidirectional FIFO Memory 44-PLCC 0 to 70
1024 X 18 asynchronous FIFO memory 80-LQFP 0 to 70
ACT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDIP24
Test-Bus Controllers IEEE Std 1149.1 (JTAG) TAP Masters With 16-Bit Generic Host Interfaces 44-PLCC -40 to 85
