
3.3V PLL Clock Driver with 1/2x, 1x and 2x Frequency Options 28-SSOP 0 to 70

High Performance, Low Phase Noise, Low Skew Clock Synchronizer that Synchronizes Ref Clock to VCXO 64-BGA -40 to 85

Low-jitter PLL-based multiplier & divider with programmable delay lines down to sub 10 ps 24-SSOP -40 to 85
1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications 40-VQFN -40 to 85

1:3 LVPECL Clock Buffer & Addl LVCMOS Output & Programmable Divider 24-VQFN -40 to 85
3.3V Phase Lock Loop Clock Driver with 3-State Outputs 48-TSSOP 0 to 70