100LVEL SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO20, SOP-20
IC LINE RECEIVER, PDSO8, PLASTIC, TSSOP-8, Line Driver or Receiver
ECL 4-Input OR/NOR Gate, SOIC-8, 0.47ns Prop Delay
100LVEL SERIES, 4-INPUT OR/NOR GATE, PDSO8, PLASTIC, TSSOP-8
100LVEL SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, PLASTIC, TSSOP-8
100LVEL SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20, SOIC-20
QUAD LINE RECEIVER, PDSO20, SOP-20
Low Skew Clock Driver, 100LVEL Series, 3 True Output(s), 0 Inverted Output(s), ECL, PDSO20, PLASTIC, SOIC-20
2-Ch LVPECL to LVTTL Translator, 180MHz, SOIC-8
3.3 V ECL ÷·4 Divider, DFN8 2.0x2.0x0.9mm, 0.5p, 1000-REEL
Differential Receiver, DFN8 2.0x2.0x0.9mm, 0.5p, 1000-REEL
2-Bit LVTTL/LVCMOS to LVPECL Translator, 350MHz, SOIC-8
ECL Dual Differential Clock/Data D Flip-Flop with Set and Reset, SOIC-20 WB, 1000-REEL
3.3 V ECL ÷2 Divider, DFN8 2.0x2.0x0.9mm, 0.5p, 1000-REEL
ECL Low Impedance Driver, DFN8 2.0x2.0x0.9mm, 0.5p, 1000-REEL
DUAL TTL/CMOS TO PECL TRANSLATOR, COMPLEMENTARY OUTPUT, PDSO8, PLASTIC, TSSOP-8
Translator, Dual LVTTL / LVCMOS to Differential LVPECL, DFN8 2.0x2.0x0.9mm, 0.5p, 1000-REEL
Clock / Data Fanout Buffer, 1:3 Differential, Dual ECL, 3.3 V, SOIC-20 WB, 1000-REEL
ECL 4-Input OR/NOR Gate, TSSOP 8 3.0x3.0x0.95 mm, 2500-REEL
Translator, Triple PECL Input to LVPECL Output, SOIC-20 WB, 1000-REEL
