Quad integrated communications controller combines a CPU32+ processor core, system integration logic, and a RISC communications processor module on one device. The controller supports operation up to 33 MHz, a 32-bit data bus, 32 address lines, and dynamic bus sizing for 8-bit and 16-bit interfaces. Its communications resources include four SCCs, two SMCs, one SPI, two TDM channels, four baud-rate generators, 14 serial DMA channels, and 2.5 KB of dual-port RAM. The device includes an eight-bank memory controller with DRAM support, four general-purpose timers, two independent DMA controllers, low-power stop mode, and an IEEE 1149.1 test access port.
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| Product type | Quad Integrated Communication Controller |
| Processor core | CPU32+ |
| Core architecture | 32bit |
| Maximum operating frequency | 33MHz |
| Data bus width | Up to 32bit |
| Address lines | 32 |
| Serial channels | 7 |
| Serial communication controllers | 4 |
| Serial management controllers | 2 |
| Serial peripheral interface | 1 |
| TDM channels | 2 |
| Dual-port RAM | 2.5KB |
| Serial DMA channels | 14 |
| Independent DMA controllers | 2 |
| General-purpose timers | Four 16-bit timers or two 32-bit timers |
| Memory controller banks | 8 |
| Ethernet support | IEEE 802.3 optional on SCCs 1-2 at 25 MHz and SCCs 1-3 at 33 MHz |
| Test access port | IEEE 1149.1 |
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Application note detailing how to interface multiple MC68360 communications controllers in a master-slave configuration to increase available serial channels.
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