
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 20-LCCC -55 to 125

High Speed CMOS Logic Dual J-K Flip-Flops with Set and Reset, Negative-Edge Trigger 16-CDIP -55 to 125
JK-Type Flip-Flop Dual 2-Bit 5V 4.5-5.5V CDIP Through Hole -55°C to 125°C