
High Speed CMOS Logic Dual Negative-Edge Trigger J-K Flip-Flops with Reset 14-CDIP -55 to 125
Dual J-K Positive-Edge-Triggered Flip-Flops W/Clear And Preset 16-CDIP -55 to 125
High Speed CMOS Logic Dual Negative-Edge Trigger J-K Flip-Flops with Reset 14-CDIP -55 to 125

Dual J-K Negative-Edge-Triggered Flip-Flops With Preset And Clear 16-CDIP -55 to 125
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-CDIP -55 to 125